| 引用本文: | 李泽文,舒 磊,邓 丰,曾祥君,邓拓夫.基于全数字锁相环的电力系统高精度同步时钟[J].电力自动化设备,2015,35(7): |
| LI Zewen,SHU Lei,DENG Feng,ZENG Xiangjun,DENG Tuofu.Wholly DPLL-based synchronous clock with high precision for electric power system[J].Electric Power Automation Equipment,2015,35(7): |
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| 摘要: |
| 提出了一种基于全数字锁相环的电力系统高精度同步时钟实现方法。该方法基于卫星时钟与晶振时钟授时误差互补的特点，在卫星时钟工作正常时，利用全数字锁相环使晶振时钟跟踪卫星时钟秒脉冲的相位波动，实时消除晶振时钟的累积误差；当卫星时钟失效时，利用失效前记录的历史分频数据辨识优化分频控制参数，预测修正晶振时钟的累积误差。仿真实验结果表明，该方法实现的同步时钟具有随机误差小且累积误差小的优点，在卫星时钟失效一段时间内仍可保持较高的授时精度，可为电力系统提供精确时间同步信号。 |
| 关键词: 卫星时钟 数字锁相环 晶振 同步时钟 电力系统 通信 同步 误差 |
| DOI： |
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| 基金项目:国家自然科学基金资助项目（51207013，51377012）；湖南省重大专项项目（2012FJ1003）；湖南省自然科学杰出青年基金资助项目（2015JJ1001）；湖南省教育厅重点项目（14A002）；湖南省高校科技成果产业化培育项目（13CY008） |
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| Wholly DPLL-based synchronous clock with high precision for electric power system |
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LI Zewen, SHU Lei, DENG Feng, ZENG Xiangjun, DENG Tuofu
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Hunan Province Key Laboratory of Smart Grids Operation and Control，Changsha University
of Science and Technology，Changsha 410114，China
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| Abstract: |
| An implementation method of synchronous clock with high precision based on wholly DPLL （Digital Phase-Locked Loop） is proposed，which is based on the complementation between satellite clock and crystal clock：when the satellite clock works properly，the crystal clock follows the “second” pulse phase fluctuation of satellite clock by the wholly DPLL to eliminate the accumulated error of crystal clock in real time；when the satellite clock works improperly，the historic frequency-division data are used to identify and optimize the frequency-division control parameter for predicting and correcting the accumulated error of crystal clock. Simulative results show that：the synchronous clock implemented by the proposed method has both small random error and small accumulated error，keeps higher timing precision for a certain period after the satellite clock fails，and provides precise synchronization signals for power system. |
| Key words: satellite clock DPLL crystal synchronous clock electric power systems communication synchronization errors |
