| 引用本文: | 张炳达,靳朝,朱俊杰,张佳.关注区可变的实时仿真方法与平台[J].电力自动化设备,2021,41(3): |
| ZHANG Bingda,JIN Zhao,ZHU Junjie,ZHANG Jia.Real-time simulation method and platform with variable focus areas[J].Electric Power Automation Equipment,2021,41(3): |
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| 摘要: |
| 交直流混合电网的实时仿真既要考虑电力电子设备的开关特性，又要保证适应较大的电网规模，在实际工程中面临诸多困难。给子网络赋予动态可变的关注标志，对关注子网络采用存储压力小的节点消去法，对非关注子网络采用计算量少的线性组合法，从而保证骨架型节点电压法的实用性。在Xilinx公司的Virtex-7 FPGA VC709开发板中，采用无缝的并行化仿真计算程序对接方式和灵活的结构参数查询方法解决了现场可编程逻辑门阵列资源的紧缺问题，设计了一种关注区可变的实时数字仿真平台。以典型的交直流混合电网为例，仿真验证了所提方法的可行性与所研发平台的有效性。 |
| 关键词: 交直流混合电网 实时仿真 骨架型节点电压法 关注区可变 现场可编程逻辑门阵列 |
| DOI：10.16081/j.epae.202101010 |
| 分类号:TM743 |
| 基金项目:国家自然科学基金资助项目(51477114) |
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| Real-time simulation method and platform with variable focus areas |
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ZHANG Bingda, JIN Zhao, ZHU Junjie, ZHANG Jia
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Key Laboratory of Smart Grid of Ministry of Education, Tianjin University, Tianjin 300072, China
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| Abstract: |
| The real-time simulation of AC/DC hybrid power grid should not only consider the switching characteristics of power electronic equipment, but also ensure to adapt to larger-scale power grid, which faces a lot of difficulties in the actual projects. In order to ensure the practicability of the essential node voltage method, a dynamic variable attention mark is given to the sub-network. The node elimination method with low storage pressure is adopted in the focus sub-network, while the linear grouping method with less computation is adopted in the non-focus sub-network. In the Virtex-7 FPGA VC709 development board of Xilinx Company, the shortage of FPGA(Field Programmable Gate Array) resources is solved by using the seamless parallel simulation program docking method and the flexible structural parameter query method, and a real-time digital simulation platform with variable focus area is designed. Taking a typical AC/DC hybrid power grid as the example, the feasibility of the proposed method and the effectiveness of the developed platform are verified. |
| Key words: AC/DC hybrid power grid real-time simulation essential node voltage method variable focus areas FPGA |
