| 引用本文: | 张园园,吴宁,周磊,周芳,葛芬.通用高精度时钟同步单元的设计方案[J].电力自动化设备,2018,(12): |
| ZHANG Yuanyuan,WU Ning,ZHOU Lei,ZHOU Fang,GE Fen.Design scheme of universal high-precision clock synchronization unit[J].Electric Power Automation Equipment,2018,(12): |
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| 摘要: |
| 根据对时钟同步装置守时误差的分析，提出了一种通过降低测量误差进一步提高守时精度的同步时钟装置设计方案。该方案利用时钟内插方法降低全球定位系统(GPS)秒脉冲周期测量误差，对秒脉冲均值进行余数补偿消除均值计算中的引入误差，从而提高同步时钟装置的守时精度。根据所提方案设计了基于AMBA APB总线的通用高精度同步时钟知识产权(IP)核，并利用ARM Cortex-M0内核在现场可编程门阵列(FPGA)中构建了具有高精度同步时钟IP的片上系统(SoC)进行测试验证。测试结果表明，基于所提方案设计的通用高精度同步时钟IP核所生成的同步时钟精度在20 ns以内，守时误差在每小时300 ns以内。 |
| 关键词: 同步时钟 守时 时钟内插 余数补偿 通用 IP核 片上系统 |
| DOI：10.16081/j.issn.1006-6047.2018.12.032 |
| 分类号:TM761 |
| 基金项目:国家自然科学基金资助项目(61376025,61774086)；江苏省自然科学基金资助项目(BK20160806) |
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| Design scheme of universal high-precision clock synchronization unit |
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ZHANG Yuanyuan1, WU Ning1, ZHOU Lei2, ZHOU Fang1, GE Fen1
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1.College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 211106, China;2.College of Information Engineering, Yangzhou University, Yangzhou 225127, China
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| Abstract: |
| According to the analysis of time-keeping error generated by synchronous clock device, a design scheme of the synchronous clock device is proposed, which improves time-keeping accuracy through reducing the measurement error. In order to improve the time accuracy of synchronous clock device, the interpolating clock method is adopted to reduce the measurement error of GPS(Global Position System) pulse per second period and the remainder of the mean value of pulse per second is compensated to remove the importing error in mean value calculation. The IP(Intellectual Property) core of high-precision synchronous clock based on AMBA APB bus is designed by the proposed scheme and tested by a SoC(System on Chip) with high-precision synchronous clock constructed by ARM Cortex-M0 in FPGA(Field Programmable Gate Arrays). The testing results indicate that the time synchronization accuracy of the IP core with high-precision synchronous clock designed by the proposed scheme is less than 20 ns and its time-keeping error is within 300 ns per hour. |
| Key words: synchronous clock time-keeping interpolated clock remainder compensation universal IP core SoC |
